Methods and apparatus are provided for implementing a semiconductor device with a debug core separate from a processor core. The user configurable debug core can be customized to include one or more debug core submodules. Each debug core submodule is generally associated with a particular debug feature such as trace generation, performance counters, or hardware triggers. The debug core can be driven through a variety of interfaces to allow debugging, monitoring, and control of processor operations.

 
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> Method and system for dynamic distributed data caching

> Systems and methods for providing conflict handling for peer-to-peer synchronization of units of information manageable by a hardware/software interface system

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