The invention provides a cache device and method for performing a cache process on a cache memory having a high capacity in a high speed. The cache processing section performs a cache process composed of two-stage processes, a query process (P1) and a subsequent process (P2). In the query process (P1), the respective index tables and the identifier table are used to query whether the target identifier is present in the cache memory at a step (S101). If it is present, a data address of the target identifier in the cache memory is transmitted to the CPU. Otherwise, a data address of an identifier for a previously prepared ultimate LRU in the cache memory is transmitted to the CPU at a step (S102). In a subsequent process (P2), adjustment operations for the respective tables, regarding insertion of an identifier for a new data and deletion of the identifier for the ultimate LRU data, are performed at a step (S201).