A look ahead column redundancy circuit provides high speed memory access
to both regular memory arrays and redundant memory arrays. In the
preferred embodiment of the present invention, the information on both
the address bus and the information on the next address bus are decoded
by redundant column decoders in parallel. The decoded information from
the redundant column decoders is then provided to a redundancy column
pathway as the addressing information from the address bus and the next
address bus is provided to a main column pathway. The information on the
address bus is latched when beginning at a new column address. The
information on the next address bus is latched for the next column
address when operating in a burst cycle mode. The main column pathway
preferably includes a latch, a main column decoder and a main column
select circuit. A disable signal is also activated by the redundant
column decoders if the addressing information for a current memory access
operation corresponds to an address within the redundant memory array.
When activated, the disable signal disables the main column select
circuit within the main column pathway. If the addressing information for
a current memory access operation does not correspond to an address
within the redundant memory array, then the memory access operation is
performed within the main memory array without any delays. Since the
decoding is performed before the information is latched onto the column
address bus, the proper pathway is selected without the need for any
additional delay.