Methods, systems and program products for evaluating an IC chip are
disclosed. In one embodiment, the method includes running a statistical
static timing analysis (SSTA) of a full IC chip design; creating
at-functional-speed test (AFST) robust paths for an IC chip, the created
robust paths representing a non-comprehensive list of AFST robust paths
for the IC chip; and re-running the SSTA with the SSTA delay model setup
based on the created robust paths. A process coverage is calculated for
evaluation from the SSTA runnings; and a particular IC chip is evaluated
based on the process coverage.