Methods of fabricating nonvolatile memory devices are provided. An isolation layer is formed on a substrate. The substrate has a memory region and a well contact region and the isolation layer defines an active region of the substrate. A gate insulating layer is formed on the active region. The gate insulating layer is patterned to define an opening therein. The opening exposes at least a portion of the well contact region of the substrate and acts as a charge pathway for charges generated during a subsequent etch of the isolation layer. Related memory device are also provided.

 
Web www.patentalert.com

< Dummy patterns and method of manufacture for mechanical strength of low K dielectric materials in copper interconnect structures for semiconductor devices

> Semiconductor package and method of manufacturing the same

> Intra-chip power and test signal generation for use with test structures on wafers

~ 00552