A semiconductor memory device includes a memory cell core having a plurality of memory cells; a data input/output circuit unit, which sets an input/output data width in response to input/output control signals and inputs/outputs data signals through at least some of a plurality of input/output pads; a pipelined circuit unit, which is connected to the data input/output circuit unit through input/output lines and transmits the data signals between the memory cell core and the data input/output circuit unit in synchronization with predetermined clock signals through an input/output path selected in response to pipeline enable signals; and a plurality of selection units, which are connected to the input/output lines through external common data lines and connect some of the input/output lines to the data input/output circuit unit in response to selection control signals. The semiconductor memory device and the data input/output method enable selective changes to the input/output data width, as needed, and selectively operate a pipelined circuit based on a set input/output data width.