A voltage regulator may include a resistor-based voltage divider circuit generating a desired output voltage from a supply voltage, an output NMOS device whose source terminal may be configured as the output of the voltage regulator and whose drain terminal may be configured to receive the supply voltage, and a control circuit configured to control the output NMOS device to maintain the desired output voltage at the output of the voltage regulator. The control circuit may be configured to receive the desired output voltage from the voltage divider circuit as a first input, and to receive the output of the voltage regulator fed back as a second input to form a feedback loop. The control circuit may control the gate of the output NMOS device via the feedback loop to adjust the output of the voltage regulator by maintaining the desired output voltage at the source of the output NMOS device, and may also clamp the output of the voltage regulator to a specified voltage that is lower than the supply voltage, without requiring a second feedback loop.