A method, system, and computer program product for enhancing performance
of an in-order microprocessor with long stalls. In particular, the
mechanism of the present invention provides a data structure for storing
data within the processor. The mechanism of the present invention
comprises a data structure including information used by the processor.
The data structure includes a group of bits to keep track of which
instructions preceded a rejected instruction and therefore will be
allowed to complete and which instructions follow the rejected
instruction. The group of bits comprises a bit indicating whether a
reject was a fast or slow reject; and a bit for each cycle that
represents a state of an instruction passing through a pipeline. The
processor speculatively continues to execute a set bit's corresponding
instruction during stalled periods in order to generate addresses that
will be needed when the stall period ends and normal dispatch resumes.