An exemplary circuit for regulating a timing sequence of a computer includes a PWM chip, a north bridge, a converting circuit, and a CPU. The PWM chip is connected to a power supply via a first resistor, and sends out a PWRGD_VRD signal and three-phase voltage signals. The north bridge outputs a PWRGD_CPU signal according to the PWRGD_VRD signal. The converting circuit transforms the three-phase voltage signals to a Vccp signal. The CPU sends out a VTT_PWRGD signal based on the PWRGD_CPU signal, and receives the Vccp signal. Wherein the logic level of the PWRGD_VRD signal is pulled up by the resistor, causing the timing sequence of the PWRGD_CPU signal to advance, the timing sequence of the VTT_PWRGD signal is also advanced according to the PWRGD_CPU signal, the timing sequence of the VTT_PWRGD signal is in advance of the timing sequence of the Vccp signal.