Performing a sum of numbers operation in a variable bit-length environment of a processor in response to a summation instruction, comprising a) adding a least significant portion (LSP) of a first number to a LSP of another number from a plurality of numbers, wherein the sum is stored in a first storage location; b) incrementing an overflow counter if a carry is generated by adding the LSPs of the two numbers; c) adding a LSP of a next number from the plurality of numbers to the sum stored in the first storage location, wherein the resulting sum is stored back into the first storage location; d) incrementing the overflow counter if a carry is generated by adding the LSP of the next number to the sum in the first storage location; e) performing steps c) and d) until each of the LSPs of the plurality of numbers has been added.