An integrated circuit with an antenna and a method of forming the integrated circuit. The method includes, in an integrated circuit package, forming each bond to or from an integrated circuit pad that is intended to be an antenna connection to be elongated compared to other bonds, and arranged in an approximately perpendicular direction to the plane of the integrated circuit; encapsulating the top of the integrated circuit package with a dielectric material at a height grater than a desired antenna length; and milling the dielectric encapsulation down to a pre-selected and calibrated height, such that the elongated bond wire to/from the integrated circuit pad that is intended to be an antenna connection is severed, such that the approximately vertical bond wire to/from the integrated circuit pad that is intended to be an antenna connection forms a quarter wave monopole.

 
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> Multi-leadframe semiconductor package and method of manufacture

> Semiconductor device with non-overlapping chip mounting sections

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