A residue block in a stage of a pipeline ADC processing differential
signals contains multiple pairs of capacitors. During a hold phase of
operation, one capacitor of a pair is connected to a positive reference
voltage, and the other capacitor is connected to a negative reference
voltage if the input signal exceeds a corresponding threshold voltage.
When the input signal does not exceed the corresponding threshold
voltage, both capacitors of the pair are connected either to the positive
or the negative reference voltage. As a result, the need for a common
mode reference voltage may be eliminated, and the residue block can be
implemented with a smaller area.