A power-on reset circuit includes a first PNP transistor having an emitter, a base, and a collector coupled to ground; a second PNP transistor having an emitter coupled to the base of the first transistor, and a base and collector coupled to ground; a third PNP transistor having an emitter, a base coupled to the base of the first transistor, and a collector coupled to ground; a first resistor coupled between VDD and an internal node; a second resistor coupled between VDD and the emitter of the first transistor; a third resistor coupled between the internal node and the emitter of the third transistor; and a comparator having a first input coupled to the internal node and a second input coupled to the emitter of the first transistor for generating a power-on reset signal.