A data processing system comprises a processor to process instructions. A
plurality of pipeline stages to execute instructions including a register
file. The register file includes a memory unit having a plurality of
memory locations, each memory location being addressable by an encoded
address. The encoded address corresponds to at least one register and
processing mode. Input ports receive inputs for addressing at least one
of the memory locations using an encoded address. Output ports to output
data from at least one of the memory locations using an encoded address.