For accomplishing a circuit design, a first physical design is implemented
according to a first netlist to obtain a first physical layout of a
circuit. The first physical layout of the circuit is processed to obtain
a first timing data. The first timing data is then inputted for timing
verification of the first netlist. If the first netlist does not pass the
verification, the first netlist is modified into a second netlist, while
defining a modified portion of the netlist. Then, the modified portion of
netlist is processed to obtain a second timing data, and the second
timing data is used to overwrite a part of the first timing data. The
first physical design is modified into a second physical design according
to the second netlist only when the second netlist with the first timing
data overwritten by the second timing data passes the timing
verification, thereby improving time efficiency.