A computer (12) having multiple data paths (38a-d) connecting to other
devices, which may be similar computers. A register (40d) is provided
that has bits (110) programmatically settable to address each of the data
paths such that the computer can communicate via multiple of the data
paths based on which bits are concurrently set in the register. The bits
respectively represent instances of the other devices as source devices
that the computer can read data from and instances of the other devices
as destination devices that the computer can write data to. A single
address in the register can represent both a source device and a
destination device for data communicated by the computer. Optionally,
multiple of the computers can be connected in series (termed a pipeline)
or to form an array (10).