An LED chip of the present invention has a structure in which an n-type semiconductor layer and a p-type semiconductor layer are successively formed on the lower face of an element substrate, with the p-type semiconductor layer being formed on an area except for an area for an n-electrode. A first n-electrode is formed on the area for the n-electrode and a first p-electrode is formed on the p-type semiconductor layer. A first insulating layer having openings and is formed on the first n-electrode and the first p-electrode, and a second n-electrode and a second p-electrode having virtually the same size are formed on the first insulating layer. With this arrangement, the electrode on the n-type semiconductor layer can be made larger, thereby a mounting process of LED chips onto a circuit board can be executed by using solder at low costs.

 
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> Integrated circuit including spacer defined electrode

> Method of manufacturing a strained semiconductor layer, method of manufacturing a semiconductor device and semiconductor substrate suitable for use in such a method including having a thin delta profile layer of germanium close to the bottom of the strained layer

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