Floating trenches are arranged in the layout of a single DMOS transistor or an array of DMOS transistors, the array forming a single power transistor. The trenches run perpendicular to the gate width direction either outside the transistor(s) or between rows of the transistors. The floating trenches are at a potential between the drain voltage and the substrate voltage (usually ground). The potentials of the opposing trenches cause merging depletion regions in the drift region. This merging shapes the field lines so as to increase the breakdown voltage of the transistor and provide other advantages. The technique is applicable to both lateral and vertical DMOS transistors.