A semiconductor memory test device and method thereof are provided. The
example semiconductor memory test device may include a fail memory
configured to store at least one test result of a memory under test, a
mode selecting unit configured to output a selection signal for selecting
a memory address protocol of the fail memory based upon which one of a
plurality of test modes is active in the memory under test and an address
arranging unit configured to arrange address signals to conform with the
selected memory address protocol in response to the selection signal
received from the mode selecting unit.