Floating gate structures are disclosed which have a base field coupled
with the substrate and a narrow projection extending from the base away
from the substrate. In one form, surfaces of a relatively large
projection provide an increased surface area for a control gate that
wraps around it, thereby increasing the coupling between the two. In
another form, an erase gate wraps around a relatively small projection in
order to take advantage of sharp edges of the projection to promote
tunneling of electrons from the floating to the erase gate. In each case,
the control or floating gate is positioned within the area of the
floating gate in one direction, thereby not requiring additional
substrate area for such memory cells.