A system for designing a semiconductor integrated circuit includes an extraction module for extracting through wiring tracks linearly passing through each of area priority cells and yield priority cells, a layout data generator for generating second layout data from first layout data by replacing the area priority cells with the yield priority cells; and a calculator for calculating a ratio of the number of intersections at which through wiring cannot be laid to the number of all of the intersections defined in the semiconductor integrated circuit.

 
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