Disclosed is a memory controller which is disposed between a CPU and a memory, receives from the CPU a control signal (TRANS) indicating whether a type of a bus cycle is a sequential cycle in which an address continuous with an address of an immediately preceding bus cycle is output to the memory as an address of a current bus cycle or a nonsequential cycle in which an address unrestricted by the address of the immediately preceding bus cycle is output to the memory as an address of a current bus cycle. The memory controller outputs a control signal (RDY) for notifying completion of the bus cycle to the CPU. In this memory controller, an address assuming the sequential cycle is generated in advance from the current address before completion of the bus cycle. Then, the address assuming the sequential cycle is supplied to the memory in a next cycle. Read data from the memory corresponding to the address assuming the sequential cycle is then output to the CPU. At this occasion, when data on an address corresponding to the nonsequential cycle should be originally supplied, the RDY signal is deactivated. As a result, the read data is not taken in by the CPU, and the read data is invalidated.