A method for reducing leakage current within a register file of a processor is disclosed. The register file within the processor is partitioned into at least two power domains, and each of the two power domains can be powered independently. At least one of the two power domains includes at least as many physical registers as there are architected registers defined in an instruction set architecture of the processor. In response to an occurrence of an idle condition within the processor, all architected register file entries are consolidated into one of power domains that will not be powered off, and the power domains that does not contain any architected register file entries after consolidating are powered off. Afterwards, in response to a detection of an end of the idle condition, all of the power domains are powered back on.

 
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> Removable storage device and method of data recovery using the same

> Storage controller and data management method

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