Errors in an analog to digital converter that cause generated digital codes to deviate from expected values are corrected. A sample of an analog signal is stored in a storage element. An error signal is then generated, with the error signal representing a deviation of an expected digital code for the strength of a sample of an analog input from a value that would be generated without correction. The error signal is then added to the stored sample. In an embodiment implemented in the context of a SAR ADC, a digital value representing an integral non-linearity error is generated based on a partial digital code (result of a partial conversion of the sample) and an error coefficient. The digital value is converted to analog form by an auxiliary DAC, and added to the stored input sample.