Disclosed is a memory device including an error rate measurement circuit
and a control circuit. The error rate measurement circuit, carrying a
BIST circuit, reads out and writes data for an area for monitor bits
every refresh period to detect an error rate (error count) with the
refresh period. The control circuit performs control for elongating and
shortening the refresh period so that a desired error rate will be
achieved. The BIST circuit issues an internal command and an internal
address and drives the DRAM from inside. The BIST circuit writes and
reads out desired data, compares the monitor bits to expected values
(error decision) and counts the errors.