Architecture for compact multi-ported register file is disclosed. In an
embodiment, a register file comprises a single-port random access memory
(RAM). The single-port RAM comprises a single port for read operations
and for write operations. Either a single read or a single write
operation is performed for a given clock via the single port. Moreover,
the single-port RAM serially performs N read operations and M write
operations associated with a data group using a clock phase of (N+M)
clock phases generated from a clock. In another embodiment, a
semiconductor device includes the architecture for compact multi-ported
register file. The semiconductor device comprises a plurality of register
files. Each register file comprises a RAM comprising a port for read
operations and for write operations. Moreover, each RAM serially performs
N read operations and M write operations associated with one of a
plurality of data groups using a corresponding clock phase of (N+M) clock
phases generated from a clock. Further, the semiconductor device
comprises an input staging unit for staging write data of one or more of
the write operations. Continuing, the semiconductor device comprises an
output staging unit for staging read data of one or more of the read
operations. The semiconductor device can be a graphics processing unit
(GPU).