A thin film transistor array panel including a substrate; a gate line formed on the substrate; a gate insulating layer formed on the gate line; a semiconductor layer formed on the gate insulating layer; a data line formed on the semiconductor layer; a drain electrode separated from the data line and formed on the semiconductor layer; a coupling electrode connected to the drain electrode; a first subpixel electrode connected to the drain electrode; and a second subpixel electrode separated from the first subpixel electrode and overlapping the coupling electrode.