A method for determining placement of circuitry during integrated circuit design. The method includes accessing a net list identifying circuitry connections. A plurality of individual net weights are assigned to nets in timing paths within the net list, the individual net weights being valid irrespective of physical design parameters. A composite net weight is determined for said timing paths, the composite net weight being in response to the plurality of individual net weights. Initial placement of the circuitry is determined in response to the composite net weight.

 
Web www.patentalert.com

< Receiver circuit for on chip timing adjustment

> Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations

~ 00495