Mechanisms for modeling metastability decay through latches in an
integrated circuit model are provided. Asynchronous clock boundaries are
identified in the integrated circuit model and latches in a receive clock
domain are enumerated. Latches within a range of the asynchronous clock
boundary are selected for transformation. These latches are transformed
into metastability decay latches using new latch primitive logic that
models the decay of an indeterminate value. The metastability decay
latches maintains an indeterminate value during a metastability time
period and achieve a randomly selected logic value at the end of the
metastability time period. The transformed integrated circuit model may
then be simulated and the results analyzed to generate reports of the
integrated circuit model's operation. The transformed integrate circuit
model more accurately represents the actual operation of the hardware
implementation of the integrated circuit model.