A power-optimized analog-to-digital converter (ADC) input circuit provides for optimized power consumption versus performance. The first amplifier stage of the ADC is provided by a plurality of amplifiers that are selectably enabled to provide a particular bandwidth and noise performance level. The selection of the combination of enabled amplifiers may be made in conformity with the sample rate of the converter and the amplifiers may have evenly-weighted bias currents, or unevenly weighed bias currents and may be optimized for their particular use in combinations for bandwidth and 1/f noise corner performance. The outputs of the amplifiers are combined in a combiner circuit, which may be a discrete-time chopping amplifier that receives charges from a plurality of capacitors that sample each enabled amplifier output.

 
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> Successive approximation A/D converter comparing analog input voltage to reference voltages

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