Techniques are disclosed for determination of parameter variability for one or more given interconnects of a plurality of interconnects in a simulated semiconductor circuit. The simulated semiconductor circuit is defined at least in part by a plurality of input parameters. From a distribution of first values of a given input parameter, a plurality of the first values are determined to use when calculating a corresponding plurality of second values for each of one or more output parameters. By using at least the determined plurality of first values for the given input parameter and selected values for other input parameters in the plurality of input parameters, the corresponding plurality of second values are calculated for each of the one or more output parameters. The one or more output parameters correspond to the one or more given interconnects. Each of the second values corresponds to one of the determined plurality of first values.

 
Web www.patentalert.com

< Spin transfer MRAM device with novel magnetic free layer

> Membrane 3D IC fabrication

~ 00491