A power delivery system for a microprocessor or other ASIC. The power delivery system includes a plurality of cascaded buck stages connected in series, wherein a last buck stage in the plurality of cascaded buck stages provides an output voltage V.sub.o in response to an input voltage V.sub.in applied to a first buck stage of the plurality of cascaded stages. A duty cycle control regulates a duty cycle of each buck stage to maintain the output voltage V.sub.o. The duty cycle control sets the duty cycle of the first buck stage of the plurality of cascaded buck stages to 1 if an input-to-output voltage ratio (V.sub.in/V.sub.o) is lower than a threshold input-to-output voltage ratio R.sub.T.