A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between a processing element and a memory system such that write data is buffered and information based upon both reads and writes is recorded. Information is maintained allowing the detection of memory conflicts. The packet processor implements a checkpoint repair mechanism allowing processing to restart from defined checkpoints. In some embodiments this is done with sub-sequence numbers. When a memory conflict is detected a restart signal is generated to backup and restart from a given checkpoint.

 
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> Memory reclamation with optimistic concurrency

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