A data recovery circuit employing an oversampling technique. The incoming
serial data stream with jitter is oversampled by means of the multiple
phases of a reference clock to produce data samples. Each sample is
compared to the samples collected with the next clock phase in an edge
detector circuit to determine the presence of a data edge. The edge
information, representative of the data edge positions, is stored and
accumulated in the form of a bit map. A detection/suppression circuit
detects and suppresses edges which are not adjacent to any other edge in
the edge memory. A selection determination circuit uses the edge
information to indicate which sample is the farthest from the data edges.
A selection validation circuit validates the selection to avoid false
determination due to jitter and skew.