A method of forming a planar CMOS transistor divides the step of forming
the gate layer into a first step of patterning a resist layer with a
first portion of the gate layer pattern and then etching the polysilicon
with the pattern of the gates. A second step patterns a second resist
layer with the image of the gate pads and local interconnect and then
etching the polysilicon with the pattern of the gate pads and local
interconnect, thereby reducing the number of diffraction and other
cross-talk from different exposed areas.