A Three-Dimensional Structure (3DS) Memory allows for physical separation
of the memory circuits and the control logic circuit onto different
layers such that each layer may be separately optimized. One control
logic circuit suffices for several memory circuits, reducing cost.
Fabrication of 3DS memory involves thinning of the memory circuit to less
than 50 .mu.m in thickness and bonding the circuit to a circuit stack
while still in wafer substrate form. Fine-grain high density inter-layer
vertical bus connections are used. The 3DS memory manufacturing method
enables several performance and physical size efficiencies, and is
implemented with established semiconductor processing techniques.