A processing unit for a multiprocessor data processing system includes a
processor core and a lower level cache including a reservation logic that
records reservations of the processor core. The reservation logic passes
or fails store-conditional operations received from the processor core
based upon whether the processor core has reservations for target store
addresses of the store-conditional operations. The processor core
includes a store-through upper level cache, a reservation register, and
sequencer logic that, by reference to the reservation register, fails a
store-conditional operation without communication with said reservation
logic.