A systematic method and system for behavioral transformations for hardware synthesis and code optimization in software compilation based on Taylor Expansion Diagrams. The system can be integrated with any suitable architectural synthesis system. It can also be built into a compiler tool for general purpose processor or into a specific target compiler. For hardware synthesis, an arithmetic expression of the computation is extracted from the behavioral-level HDL design or directly from its matrix representation, and represented in canonical data structure, called Taylor Expansion Diagram. In architectural synthesis, factorization, common sub-expression extraction and decomposition of the resulting Taylor Expansion Diagram is performed, producing an optimized data flow graph, from which the structural HDL design is obtained using standard architectural synthesis. For software compilation and code optimization, common sub-expression extraction and factorization serve as pre-compilation optimization tasks performed according to the target architecture to generate a new code for the compiler.