A processor generating a histogram of a set of data values receives a data value, and sets a corresponding register in each of two sets of registers based respectively on a decoded value represented by bits in a first and second set of positions in the received data value. The processor then simultaneously increments/updates each of multiple frequency counters (specifying frequency of occurrence of respective data values/ranges) by a value of a corresponding register in one of the two sets of registers if a value of a corresponding register in the other one of the two sets of registers is set. As a result, histogram generation is made efficient and fast. In an embodiment, 32 frequency counters are updated in 16 operations.