The invention provides a semiconductor memory device that includes at least two memory banks. The semiconductor memory device is designed in such a way that: at least two processor units can carry out read accesses and write accesses to memory banks; and by means of an inhibit command communicated by one of the processor units, the write access by the processor unit which has communicated the inhibit command and/or by at least one of the other processor units to the inhibited memory bank is prevented at least occasionally. A circuit arrangement including the above semiconductor memory device is furthermore proposed.