Diode-based capacitor memory uses relatively small capacitor, and uses a
diode as an access device instead of MOS transistor, wherein the diode
has four terminals, the first terminal is connected to a word line, the
second terminal is connected to the first plate of capacitor which serves
as a storage node, the third terminal is floating, the fourth terminal is
connected to a bit line, wherein the capacitor is formed between the
first plate and the second plate, and a plate line is connected to the
second plate, during write the storage node is coupled or not, depending
on the state of the diode by changing the plate line, during read the
diode serves as a sense amplifier as well to detect the storage node
voltage whether it is forward bias or not, in this manner the capacitor
does not drive heavily loaded bit line directly, instead, it drives
lightly loaded second terminal, and then the diode sends binary results
to a data latch including a current mirror which repeats the amount of
current that the memory cell flows, and the word line is de-asserted to
cut off the holding current during standby, in addition its applications
are extended to single port and content addressable memory. Furthermore,
cell structures are devised on the bulk or SOI wafer.