A programmable logic device has programmable phase-shifting circuitry. The
phase-shifting circuitry is used to generate a set of skewed clock
signals that is used to adjust the relative timing of device elements in
a circuit synthesized in the programmable logic device. By suitably
adjusting the relative timing of the device elements, the circuit
critical path lengths are effectively reduced leading to improved circuit
frequency performance. Algorithms are provided for establishing clock
skew values that lead to improved circuit performance. The algorithms are
incorporated in computer aided design tools to enable automatic
optimization of circuit designs.