Some embodiments provide a device under test comprising a processing core
to support execution debug signals, a debug ring to receive and to
transmit the execution debug signals from and to the device under test, a
first debug port to receive and transmit the execution debug signals from
and to the debug ring, and a second debug port to receive data from
observation signal lines of the device under test. The first debug port
may transmit execution debug signals to define an event to detect within
the device under test, to receive execution debug signals indicating
occurrence of the event, and to use a handler to place the device under
test in a quiescent state and to instruct the device under test to
transmit data of one or more registers. The second debug port may receive
the data of the one or more registers from observation signal lines of
the device under test.