In at least one hardware definition language (HDL) file, at least one
design entity containing a functional portion of a digital system is
specified. The design entity logically contains first and second latches
each having a respective plurality of different possible latch values.
With one or more statements, a first Dial instance is associated with the
first latch and a second Dial instance is associated with the second
latch. A setting of the first Dial instance thus controls which of the
plurality of different possible values is loaded in the first latch, and
a setting of the second Dial instance controls which of the plurality of
different possible values is loaded in the second latch. With a
statement, a Register instance is concurrently associated with both the
first and the second latches, such that a setting of the Register
instance controls the latch values loaded in both the first and second
latches.