A semiconductor memory apparatus which can restrict a refresh operation for a period when an internal clock is synchronized with an external clock. The semiconductor memory apparatus includes a refresh control unit that disables a refresh command signal which is applied during a period when an enable signal is enabled but a lock-completion signal is not enabled in response to the enable signal outputted from a mode register, the lock-completion signal outputted from a clock synchronizing unit, and the refresh command signal outputted from a command decoder. The clock synchronizing unit can stably complete a locking operation within a predetermined time regardless of power-supply noise and so on.