A logic simulation processor stores in a shift register intermediate
values generated during the logic simulation. The simulation processor
includes multiple processor units and an interconnect system that
communicatively couples the processor units to each other. Each of the
processor units includes a processor element configurable to simulate at
least a logic gate, and a shift register associated with the processor
element. The shift register includes multiple entries to store the
intermediate values, and is coupled to receive the output of the
processor element. Each of the processor units further includes one or
more multiplexers for selecting one of the entries of the shift register
as outputs to be coupled to the interconnect system. Each of the
processor units may further include a local memory for storing data from,
and loading the data to, the simulation processor.