In lower hierarchy design in which a plurality of circuit blocks are
independently designed, a reset adjustment circuit propagating
deactivation transition of a reset signal to flip-flops in
synchronization with a clock signal is inserted immediately after a reset
input pin in each circuit block, and timing adjustment using the clock
signal as a reference is implemented for signal paths of the reset signal
from the reset adjustment circuit to the flip-flops. In upper hierarchy
design in which an entire semiconductor integrated circuit is designed,
timing adjustment using the clock signal as a reference is implemented
for signal paths of the reset signal, according to setup times and hold
times of the reset signal that are prescribed respectively for the reset
input pins of the circuit blocks.