A sigma delta (.SIGMA..DELTA.) analog to digital converter (ADC) that
compensates for the adverse effects associated with the time delay
introduced by delay circuitry of the feedback loop. This .SIGMA..DELTA.
ADC includes a first summing stage, first integrator, second summing
stage, second integrator, quantizer, and feedback loop. The second
integrator has associated with it a feed forward pass operable to reduce
negative effects of delay circuitry within the feed back loop. Feedback
loop includes delay circuitry and a number of digital to analog
converters. The feed forward path that reduces the effects of the delay
includes a resistance within the second or additional integrator. This
allows the adverse effects of the time delays associated, which may lead
to circuit instability or meta-stability, to be reduced or eliminated.