In a processor system comprising of a processor having an instruction decoder 22, a general register 61 composed of a plurality of register areas and at least one ALU 60, and a Java accelerator 30 for converting a Java bytecode sequence to a native instruction sequence for the processor and supplying the native instruction sequence to the instruction decoder. The Java accelerator 30 is composed of a bytecode translator 40 for converting the Java bytecode sequence to the native instruction sequence for the processor and a register status control unit 50 for mapping a Java operand stack to any of the register areas of the general register and detecting a bytecode redundant for the processor. When a redundant bytecode is detected by the register status control unit 50, the supply of the native instruction from the bytecode translator 40 to the instruction decoder 22 is inhibited.

 
Web www.patentalert.com

< Volume-based network management scheme

> Placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline

~ 00467