Provided is a method for fabricating a semiconductor device having reduced contact resistance. In the method, gate patterns defining a narrow opening and a wide opening are formed having an upper portion of a predetermined region of a semiconductor substrate. After gate spacers are formed on sidewalls of the gate patterns, an ion implantation process that uses the gate patterns and the gate spacers as an ion mask is performed to form a plug doped region in a portion of the semiconductor substrate that is located below the wide opening. At this point, the gate spacers are formed to expose a portion of a bottom surface of the wide opening and to fill a lower portion of the narrow opening.